In general, in a case where image data is transferred from a host processor (hereinafter merely referred to as “host”) to a display panel such as an LCD, the image data is temporarily stored in a frame memory (hereinafter merely referred to as “memory”) in an LCDC (LCD controller) and then output to the display panel. Consequently, when display data is not updated, it is unnecessary to transfer the image data from the host.
However, in a seamless process such as video image reproduction, input (writing) of image data from the host to the LCDC (frame buffer) and output (reading) of image data from the LCDC to the display panel are carried out substantially concurrently.
Consequently, in a case where a difference in transfer rate of image data between input and output cannot be compensated completely, so-called tearing occurs, which is an overtaking phenomenon of image data, in which phenomenon incomplete image data stored in a memory is output to a display panel. Furthermore, the output of incomplete image data to the display panel in the tearing causes flickers in image display.
An example of a prior art for preventing such tearing is a frame rate changing device disclosed in Patent Literature 1. The frame rate changing device includes memory control means for inputting/outputting data into/from a common memory, overtake prediction means for predicting a frame at which output of data from the memory overtakes input of data into the memory, and memory-writing control means for stopping writing of data into the memory when the overtake prediction means predicts that overtaking will occur.
Patent Literature 2 discloses a method for updating a buffer. This is a method for carrying timing information via a communication link between a first processor and a second processor. Furthermore, in this method, the communication link is in a halt mode, and a time event is scheduled in the first processor in order to carry the timing information to the second processor. Furthermore, in this method, link wakeup is started by the first processor when the time event is generated, the second processor detects the link wakeup, and the first processor and the second processor are synchronized with each other with respect to the carried timing information with use of detected link wakeup timing.